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? e96434-te sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage v cc ?.3 to 5.5 v operating temperature ta ?5 to +125 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v cc 3.3?.165 v operating temperature ta ?0 to +85 ? description the CXA3003R is a baseband analog processing ic for dual-mode cdma/fm cellular phone. the CXA3003R interfaces between the inter-frequency section and the digital processing circuitry of the telephone. the receive circuit functions primarily convert analog if signals to the analog baseband frequency range and to convert the analog baseband signals into digital signals. transmit circuits convert digital data into analog baseband signals which are then up-convert to the if frequency range. features receive signal path includes: if to baseband down conversion built-in trim-free low-pass filter for cdma and fm built-in a/d convertor convert the rx base band signal to the digital signal analog output receive signal strength indicator (rssi) for cdma local oscillator for i-q mixer transmit signal path includes: built-in d/a convertor convert the digital i-q data to the analog baseband signal built-in trim-free low-pass filter for cdma and fm baseband to if up-conversion local oscillator for i-q mixer built-in pll for tx if built-in house keeping a/d convertor low power consumption in all modes single 3.3 v power supply applications dual-mode cdma/fm cellular telephone baseband analog processing ic for dual-mode cdma/fm cellular phone 80 pin lqfp (plastic) CXA3003R
? CXA3003R rxfmstrb fmclk rxqfmdt rxifmdt dnc dnc gnd adc vdd adc qoffset ioffset hkadvcc nc adcclk adcdt adcenbl adcin sleepb idleb fmb rxvcoout txd0 gnd esd vdd dac gnd dac nc nc dnc dnc cap2 cap1 nc tcxo4 nc nc tcxo nc lock det vdd txf gnd txf vdd synth rxqd3 rxqd2 rxqd1 rxqd0 rxid3 rxid2 rxid1 rxid0 chipx8 vdd buf gnd buff txclkb txclk txd7 txd6 txd5 txd4 txd3 txd2 txd1 gnd rxvco t1 rxvco t2 gnd rxif vdd rxif rxifb rxif rssi gnd rx vdd rx txifb txif gnd txif vdd txif fm mod tvco t2 tvco t1 pd iset pd out gnd synth fmq adc fmi adc cdma i adc cdma q adc q dac i dac 50 51 53 54 55 56 57 59 58 60 41 42 43 44 45 46 47 48 49 52 fm q rx lpf cdma q rx lpf cdma i rx lpf fm i rx lpf mode cntl vco hk adc 1/2 rssi cdma q tx lpf cdma i tx lpf fm tx lpf chip x8 1/4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vco pd 1/2 pll 61 62 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 63 64 block diagram
? CXA3003R pin description pin no. 1 2 3 4 5 6 7 8 9 10 symbol gnd rxvco ti rxvco t2 gnd rxif vdd rxif rxifb rxif rssi gnd rx vdd rx typical voltage (v) dc ac 0 v 0 v 3.3 v 2 v 2 v 0 v 3.3 v equivalent circuit 2 3 vdd rxif gnd rxif 1k 1k vdd rxif gnd rxif 7 6 250 2k 250 2k 2k 2k vdd rxif gnd rxif 8 150 description negative power supply pin. receive vco tuning pins. connected to an external lc tank circuit for setting the receive vco frequency. negative power supply pin for rxif block. positive power supply pin for rxif block. analog differential receive if input pins. analog rssi output pin. negative power supply pin for rx block. positive power supply pin for rx block.
? CXA3003R pin no. 11 12 13 14 15 16 17 symbol txifb txif gnd txif vdd txif fm mod tvco t1 tvco t2 typical voltage (v) dc ac 2.1 v 2.1 v 0 v 3.3 v 1.5 v equivalent circuit vdd txif gnd txif 12 11 400 200 400 200 vdd txf gnd txf 15 150 16 17 vdd txif gnd txif 1k 1k description analog differential transmit if output pins. negative power supply pin for txif block. positive power supply pin for txif block. analog baseband signal output pin for fm. transmit vco tuning pins. connected to an external lc tank circuit for setting the transmit vco frequency.
? CXA3003R pin no. 18 19 20 21 22 23 24 symbol pd iset pd out gnd synth vdd synth gnd txf vdd txf lock det typical voltage (v) dc ac 0.64 v 0 v 3.3 v 0 v 3.3 v equivalent circuit vdd txf gnd txf 18 150 vdd txf gnd txf 19 6.25k 150 6.25k 24 vdd synth gnd synth 150 description current of pd out setting pin. transmit synthesizer charge pump output pin. negative power supply pin for pll block. positive power supply pin for pll block. negative power supply pin for tx block. positive power supply pin for tx block. transmit if synthesizer lock detect output pin.
? CXA3003R pin no. 26 39 25 27 28 30 35 36 29 31 32 33 34 37 symbol tcxo gnd esd nc tcxo4 cap1 cap2 dnc gnd dac typical voltage (v) dc ac 2.2 v 0 v 0 v equivalent circuit 26 vdd synth gnd synth 150 20k 20k vdd dac gnd esd 29 150 31 32 vdd rx gnd rx description input pins for external clock 19.68 mhz (tcxo). negative power supply pin. don't connect pins. output pin for tcxo/4 frequency. the pins for external capacitor. don't connect any line to this pin. negative power supply pin for txda block.
? CXA3003R pin no. 38 40 to 47 48 49 50 51 52 53 to 56 57 to 60 61 62 symbol vdd dac txd0 to txd7 txclk, txclkb gnd buf vdd buf chip x 8 rxid0 to rxid3 rxqd0 to rxqd3 rxfmstrb fmclk typical voltage (v) dc ac 3.3 v 0 v 3.3 v equivalent circuit 40 41 42 43 44 45 46 47 48 49 vdd dac gnd dac 60k 52 53 54 55 56 57 59 58 60 vdd buf gnd buf vdd adc gnd adc 61 62 100k description positive power supply pin for txda block. transmit data input pins for transmit 8 bit d/a converter. txd7 is the msb. differential transmit clock input pins for transmit 8 bit d/a converter. negative power supply pin for a/d output block. positive power supply pin for a/d output block. output pin for chipx8 divider with a ratio of 512/1025xtcxo. output pins for receive cdma 4 bit a/d converter of i signal. rxid3 is the msb. output pins for receive cdma 4 bit a/d converter of q signal. rxqd3 is the msb. strobe input pin for receive fm 8 bit a/d converter. clock input pin for receive fm 8 bit a/d converter.
? CXA3003R pin no. 63 64 65 66 67 68 69 70 71 72 symbol rxqfmdt rxifmdt dnc gnd adc vdd adc qoffset ioffset hkadvcc nc typical voltage (v) dc ac 0 v 3.3 v 1.5 v 1.5 v 3.3 v equivalent circuit vdd buf gnd buf 63 64 69 70 vdd rx gnd rx 30k 142k 22k 100k 150 30k 142k 150 description q serial data output pin for receive fm 8bit a/d converter. i serial data output pin for receive fm 8bit a/d converter. don't connect any line to this pins. negative power supply pin for a/d converter block. positive power supply pin for a/d converter block. receive q channel offset adjust input pin. receive i channel offset adjust input pin. positive power supply pin for hka/d converter block. don't connect pin.
? CXA3003R pin no. 73 74 75 76 symbol adcclk adcdt adcenbl adcin typical voltage (v) dc ac 1.5 v equivalent circuit vdd buf gnd buf 73 74 vdd buf gnd buf 75 60k hkadvcc 76 gnd adc 48.5k description clock output pin for house keeping 8 bit a/d converter. serial data output pin for house keeping 8 bit a/d converter. enable input pin for house keeping 8 bit a/d converter. a/d analog input pin for house keeping 8 bit a/d converter.
?0 CXA3003R pin no. 77 78 79 80 symbol sleepb, idleb, fmb rxvcoout typical voltage (v) dc ac 0 v equivalent circuit gnd adc 78 77 79 vdd adc 150 80 vdd rxif gnd rxif description test mode switch pins. these pins control this ic function mode ( * 1). receive vco output pin connected the external pll ic. * 1 function mode function mode cdma rxtx cdma idle cdma sleep fm rxtx fm idle fm idle (transition) fm rxtx (transition) cdma sleep (transition) fmb high high high low low low low high idleb high low low high low low high high sleepb high high low high high low low low mode functions explain: 1. cdma rxtx : this mode requires everything except the fm- specific circuits to be operating. 2. cdma idle : this mode powers down all transmit circuits and fm receive. 3. cdma sleep : this mode powers down everything except the tcxo divider and tcxo/4 output driver. 4. fm rxtx : this mode powers down all cdma-specific circuits except the chipx8 synthesizer. 5. fm idle : this mode powers down all transmit and cdma receive circuits.
?1 CXA3003R electrical characteristics dc characteristics (vdd=3.3 v? %, ta=40 ? to 85 ?) item power supply current - cdma rxtx power supply current - cdma idle power supply current - cdma sleep power supply current - fm rxtx power supply current - fm idle logic high level input voltage logic low level input voltage logic high level output voltage logic low level output voltage logic input leakage current input capacitance digital input load capacitance digital output load resistance digital output symbol idd1 idd2 idd3 idd4 idd5 vih vil voh vol il cin-d cl-d rl-d condition * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 min. typ. max. unit 40 57 25 35 23ma 30 45 16 21 0.7xvdd 0.3xvdd v 2.7 0.4 ?00 100 ? 15 pf 15 100 k * 1 : logic input pins = 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 61, 62, 75, 77, 78, 79 logic output pins =52, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64, 73, 74 ac characteristics txclk/txclkb vs. txiqdata for cdma mode vdd=3.3 v? %, ta=?0 ? to 85 ? item data setup to txclk/txclkb transition data hold after txclk/txclkb transition symbol tsua tha condition min. typ. max. unit 50 ns 50 tsua tha txq data txi data txclk (input) txclkb (input) txqdata (input) txclk=4.9152mhz fig. 1 txclk/txclkb vs. txiqdata timing diagram for cdma mode chipx8 vs. rxiqdata vdd=3.3 v? %, ta=?0 ? to 85 ? item data output stable prior to chipx8 fall data hold after chipx8 fall chipx8 raise time chipx8 fall time symbol tsub thb trb tfb condition 10 % to 90 %, cload=15 pf min. typ. max. unit 20 15 ns 3 7.2 3 9.9
?2 CXA3003R tsub thd chip 8 (output) rxidata rxqdata (output) fig. 2 chipx8 vs. rxiqdata timing diagram txclk vs. rxdata for fm mode vdd=3.3 v? %, ta=?0 ? to 85 ? item data setup to txclk transition data hold after txclk transition symbol tsuc thc condition min. typ. max. unit 2.08 ? 2.08 item strobe input valid to clk falling edge strobe input valid after clk falling edge data out valid to clk rising edge data out valid after clk rising edge clk high time clk low time rxfmdata (i, q) raise time rxfmdata (i, q) fall time symbol tsud-s thd-s tsud-d thd-d tclk-hi tclk-lo trd tfd condition 10 % to 90 %, cload=15 pf min. typ. max. unit 0.69 2.08 1.38 ? 1.38 1.38 1.38 3 7.2 ns 3 9.9 tsuc thc tx data txclk (input) txclkb (input) xxxx xxxx tx data xxxx tx data (input) txclk=120khz fig. 3 txclk vs. rxdata mode timing diagram for fm fmclk, rxfmstrobe vs. rxfmdata (i, q) vdd=3.3 v? %, ta=?0 ? to 85 ?
?3 CXA3003R tclk-hi tclk-lo tsud-d thd-d thd-s tsud-s lsb+1 lsb xxx msb msb-1 lsb fmclk (input) fmrxstrobe (input) fxrxdata (i, q) (output) fmclk=360khz fmrxstrobe=40khz fig. 4 fmclk, fmrxstrobe vs. rxfmdata (i, q) timing diagram note : fm rxstrobe pulse width must be one fmclk period. adcenable & adc clk vs. adc data (vdd=3.3 v? %, ta=?0 ? to 85 ?) item enable true to first clock output enable pulse to end of conversion data out valid to clk rising edge data out valid after clk rising edge enable true pulse width output raise time output fall time symbol ten-clk tden-eoc tsue-d the-d ten-pw tre tfe condition 10 % to 90 %, cl=15 pf min. typ. max. unit 6 ? 16.8 600 ns 600 10 ? 7.2 ns 9.9 ten-pw ten-clk msb lsb the-d tsue-d tden-eoc adcenable adcclk adcdata adcclk=820khz (tcxo24) fig. 5 adcenable & adc clk vs. adc data timing diagram
vhf local oscillator vdd=3.3 v? %, ta=?0 ? to 85 ? ?4 CXA3003R item vco output frequency range lock mode charge pump output current acquisition mode charge pump output current maximum iout adjustment range acquisition mode disable frequency range phase detector output compliance voltage phase detector output impedance reference input frequency phase detector frequency reference spurs lock detect pull down voltage lock detect off leakage current phase detect unlock deviation threshold during fm rate tank circuit input impedance external vco input levels symbol fvcot icplt icpat icpmaxrt ? fadt vopdt zopdt freft fpdt rst vlldt iledt pdfhdt pdfhrt zit vext condition rset=40 k rset=40 k using rset to vary nominal output current acquisition mode initiated only by transition to any tx active mode ref.frequency/16 rload 3 10 k to vdd v o =vdd measured at txif nominal impedance into each pin min. typ. max. unit 260.76 mhz 12.4 15.5 18.6 ? 128 160 192 ?0 +40 % ? k +1 k hz 0.4 vdd?.4 v 1 m 2 m 19.68 mhz 1.23 mhz ?0 dbc 0.4 v 10 ? 12 khz 300 hz 1.5 k 2 k 2.5 k 200 600 800 mvp-p item vco output frequency range vco output voltage swing at 170 mhz tank circuit input impedance symbol fvcor vovr zir condition into 500 //5 pf load, ac coupled load nominal impedance into each pin min. typ. max. unit 170.76 mhz 100 147 mvrms 1.5 k 2 k 2.5 k receive vco vdd=3.3 v? %, ta=?0 ? to 85 ?
?5 CXA3003R cdma receive vdd=3.3 v? %, ta=?0 ? to 85 ? item input signal level cdma sinusoid single tone jammer desense input center frequency input resistance input capacitance input referred noise spurious content jammer related spurious content offset adjust gain offset adjust input impedance a/d converter linearity signal path gain accuracy, part to part signal path gain accuracy, total cdma rx residual sideband product filter attenuation gain flatness vs. frequency symbol vincdcr vinscr jdcr ficcr ricr cicr irncr sccr jrscr gadjocr ziocr ladcr ? gspcr ? gstcr rspcr fa1cr fa2cr gfcr condition 3 900 khz offset differential from each pin to gnd sum of i&q,measured from 1 khz to 630 khz total of all harmonic and non-harmonic power peak in-band spurious products full scale at nominal temp and vdd over part to part, vdd, temp 3 900 khz 3 1.2 mhz 1 khz to 630 khz min. typ. max. unit 0.9 mvrms 5.38 mvp-p 0.13 0.5 db 85.38 220.38 mhz 375 500 650 1.5 pf 70 135 ?rms ?0 ?5 dbc ?2 ?8.4 dbc ?0 ?0 ?0 %full scale/v 100 k 170 k 220 k lsb ?.6 1.6 db ?.1 2.1 21 dbc 46 50 db 48 62 2.0 dbp-p
?6 CXA3003R cdma transmit vdd=3.3 v? %, ta=?0 ? to 85 ? item output amplitude of lower sideband load resistance load capacitance output impedance spurious free dynamic range, in band spurious free dynamic range,bandedge spurious free dynamic range, out of band carrier suppression spurious free dynamic range :if harmonics signal to noise ratio,noise band1 signal to noise ratio,noise band2 output center frequency i, q gain mismatch i, q phase imbalance amplitude flatness vs. frequency, 1 khz to 630 khz symbol voct rlct clct zoct sfdr1ct sfdr2ct sfdr3ct csct sfdr5ct snr1ct snr2ct focct gerrct perrct afct condition i&q in quadrature full scale signals.at nominal vdd and temp differential from each pin to gnd i&q in quadrature, full scale signals even harmonics odd harmonics if 3 0.1 m to if?1.98 m if 3 1.98 m to if?44 m in band, measured at tx if in band, measured at tx if including sin(x)/x min. typ. max. unit 267 300 337 mvp-p 495 500 505 5pf 40 50 35 50 30 dbc 57 18 32 20 811 104 124 dbc/hz 117 124 130.38 mhz 0.2 0.8 db 2 8 degree 0.6 1.0 dbp-p cdma chipx8 vdd=3.3 v? %, ta=?0 ? to 85 ? item input frequency output frequency stabilization time symbol fic8 foc8 tsc8 condition tcxo tcxo x 512/1025 upon mode charge min. typ. max. unit 19.68 mhz 9.8304 10 ?
?7 CXA3003R fm receive vdd=3.3 v? %, ta=?0 ? to 85 ? item input signal level single tone jammer desense input center frequency input resistance input capacitance input referred noise spurious content jammer related spurious content offset adjust gain signal path gain accuracy, part to part signal path gain accuracy,total fm rx residual sideband products gain flatness vs. frequency filter attenuation symbol vinfr jdfr ficfr rifr irnfr scfr jrfr gadjfr ? gspfr ? gspfr ? gstfr rspfr gffr fa1fr fa2fr condition 60 khz offset differential from each pin to gnd sum of i&q,measured from 100 hz to 15 khz at nominal temp peak in-band spurious product at nominal vdd and temp over part to part ,vdd, temp from 100 hz to 12.2 khz >45 khz >60 khz min. typ. max. unit 1.53 mvrms 0.07 0.35 db 85.38 mhz 375 500 650 1.5 pf 38 ?rms ?6 ?2 dbc ?2 ?8.4 ?0 ?0 ?0 %full scale/v ?.3 1.3 db ?.1 2.1 27 dbc 0.4 1 dbp-p 48 68 db 60 69
?8 CXA3003R fm transmit vdd=3.3 v? %, ta=?0 ? to 85 ? item if output amplitude if load resistance if load capacitance if output impedance if signal to noise ratio, noise band1 if output amplitude variation if output amplitude drift maximum spurious content : tx if harmonics fm mod output voltage fm mod load resistance fm mod amplitude variation fm mod spurious free dynamic range, to 120 khz fm mod signal to noise ratio, 1 khz to 15 khz amplitude flatness vs. frequency, dc to 10 khz symbol voifft rlifft clifft zoft snr1ft voifvft ? voifdft sceft scoft vmodft rmodft ? vmodvft sfdrft shrfmodft afft condition at nominal vdd and temp differential from each pin to gnd if 3 0.1 m to if?44 m over part to part , vdd and temp over full vdd and temp ranges even harmonics odd harmonics full scale, nominal vdd and temp over part to part , vdd and temp two tone inputs single tone, full scale including sin (x) / x min. typ. max. unit 124 140 161 mvp-p 495 500 505 5pf 40 50 110 117 dbc/hz ?.6 1.6 db ? 1 ?0 dbc ?0.5 ? 490 575 610 mvp-p 10 k ?.2 1.2 db 40 44 87 100 dbc/hz 0.6 dbp-p tcxo vdd=3.3 v? %, ta=?0 ? to 85 ? item input frequency input amplitude input impedance tcxo divide ratio tcxo / 4 output amplitude symbol fitc vitc zitc rtdtc vo-tc condition from tcxo ac coupled into 10 k // 10 pf ac coupled load min. typ. max. unit 19.68 mhz 0.5 2 vp-p 5 k 4 1 vp-p
?9 CXA3003R rssi vdd=3.3 v? %, ta=?0 ? to 85 ? item dynamic range gain gain drift output signal level output load resistance full scale rise/fall time nominal setpoint symbol drrs grs ? gdrs vors rlrs trrs/tfrs nsprs condition at nominal temp and vdd over vdd and temp at nominal temp and vdd min. typ. max. unit 25 db 32 75 mv/db ?.6 1.6 db 0.5 2.5 v 50 k 30 ? 0.8 2.0 v hk adc vdd=3.3 v? %, ta=?0 ? to 85 ? item resolution input voltage range midscale output code error dle ile conversion time input impedance symbol reshk vihk emidhk dlehk ilehk tchk zihk condition internal voltage referenced v (adcin)=1.5 v at nominal temp and vdd min. typ. max. unit 8 bits 1.79 2 2.24 v ?6 16 code ? 1 lsb ?.25 1.25 40 ? 20 k
?0 CXA3003R electrical characteristics measurement circuit rxfmstrb fmclk rxqfmdt rxifmdt dnc dnc gnd adc vdd adc qoffset ioffset hkadvcc nc adcclk adcdt adcenbl adcin sleepb idleb fmb rxvcoout txd0 gnd esd vdd dac gnd dac nc nc dnc dnc cap2 cap1 nc tcxo4 nc nc tcxo nc lock det vdd txf gnd txf vdd synth rxqd3 rxqd2 rxqd1 rxqd0 rxid3 rxid2 rxid1 rxid0 chipx8 vdd buf gnd buff txclkb txclk txd7 txd6 txd5 txd4 txd3 txd2 txd1 0.01 1n d/a converter d/a converter pattern generator 50 51 53 54 55 56 57 59 58 60 41 42 43 44 45 46 47 48 49 52 0.01 1n pattern generator d/a converter d/a converter d/a converter serial- parallel converter serial- parallel converter serial- parallel converter 0.01 62 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 63 64 61 1n 0.01 0.01 1n 0.01 10k oscilloscope 40 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 21 0.01 0.01 1n 0.01 500 1:1 1:3 v 1:1 spectrum analyzer 10k 1:1 50 50 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 39k a gnd rxvco t1 rxvco t2 gnd rxif vdd rxif rxifb rxif rssi gnd rx vdd rx txifb txif gnd txif vdd txif fm mod tvco t2 tvco t1 pd iset pd out gnd synth CXA3003R 100k 100k 100k 100k 100k 100k 100k 100k 100k 100k 100k 1n 100k 100k 100p 1n 51k 1n 1n 1n 0.01 0.01
?1 CXA3003R rxfmstrb fmclk rxqfmdt rxifmdt dnc dnc gnd adc vdd adc qoffset ioffset hkadvcc nc adcclk adcdt adcenbl adcin sleepb idleb fmb rxvcoout txd0 gnd esd vdd dac gnd dac nc nc dnc dnc cap2 cap1 nc tcxo4 nc nc tcxo nc lock det vdd txf gnd txf vdd synth rxqd3 rxqd2 rxqd1 rxqd0 rxid3 rxid2 rxid1 rxid0 chipx8 vdd buf gnd buff txclkb txclk txd7 txd6 txd5 txd4 txd3 txd2 txd1 0.01 1n 0.01 1n 0.01 0.01 0.01 1n 0.01 0.01 1n 0.01 0.01 gnd rxvco t1 rxvco t2 gnd rxif vdd rxif rxifb rxif rssi gnd rx vdd rx txifb txif gnd txif vdd txif fm mod tvco t2 tvco t1 pd iset pd out gnd synth CXA3003R to digital processing section from digital processing section from digital processing section to digital processing section to digital processing section amp 62 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 63 64 61 pll to transmit rf circuits from receive rf circuits 50 51 53 54 55 56 57 59 58 60 41 42 43 44 45 46 47 48 49 52 40 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 100k 100k 100k 100k 100k 100k 100k 100k 100k 100k 100k 1n 100k 100k 100p 100n 56p 56p 2p 1t367 1t367 10k 10k 51k 1n 220 680p 47n 22p 22p 8p 1t367 1t367 10k 10k 0.86 1.8k 1n 22k 39k 1n 1n 0.01 0.01 1n 1n 1n application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?2 CXA3003R description of operation 1. overall operations this ic bridges the gap between the analog rf processing and digital processing sections of the cellular telephone. figure 6 illustrates the general circuit blocks in the portable cellular telephone employing this ic. the analog inputs and outputs of this ic interface directly with the if (intermediate frequency) transmit/receive circuitry of the telephone. the digital inputs and outputs of this ic interface directly with the digital processing section. the rf receive circuitry acquires the low-level forward link signal from the base station (cell site) and down-converts to the if frequency band. the rf transmit circuitry takes cdma or fm modulated analog if from this ic, up-converts to the channel frequency, and outputs controlled reverse link power levels to the antenna. the digital processing section includes cdma modulation/demodulation , digital fm modulation/demodulation, voice processing, and a keypad interface. the codec (coder-decoder) block interfaces the telephone microphone and earpiece to the digital processing section. this ic receive signal path down-converts the acquired if signal to baseband where it is then converted to digital data. the digital baseband signals are sent to the digital processing section for demodulation. when transmitting, the digital processing section sends modulated digital baseband signals to this ic for up-conversion to the analog if frequency. this ic consists of a receive signal path, a transmit signal path, clock synthesis and buffering circuits, mode control logic, and a house keeping analog-to-digital converter (adc). fig. 6 dual-mode cdma/fm cellular telephone block 2. cdma receive signal path this ic receive signal path (see fig.7) is designed to accept a differential if signal with cdma spread spectrum modulation extending ?30 khz from the if center frequency of 85.38 mhz. the incoming if is reduced to i and q baseband components by mixing with 85.38 mhz local oscillator (lo) signals in quadrature followed by low-pass filtering. the 85.38 mhz i and q lo signals are generated on this ic. the receive vco is set 170.76 mhz by an external varactor-tuned resonant tank circuit (inductor l and capacitor c connected in parallel). an external phase-lock loop and loop filter network provide the feedback to the varactors which tune the vco to 170.76 mhz. a master-slave divide-by-two circuit generates i and q signals in precise quadrature for the mixers. rf transmit/ receive processing the digital processing mobile station modem codec CXA3003R baseband analog processor antenna
?3 CXA3003R fm q rx lpf fm i rx lpf cdma q rx lpf cdma i rx lpf chip x8 1/4 fm q adc fm i adc cdma q adc cdma i adc rssi rxqfmdata rxifmdata rxqd3 rxqd2 rxqd1 rxqd0 rxid3 rxid2 rxid1 rxid0 rssi chipx8 tcxo4 1/2 vco rxfmstrobe fmclk qoffset ioffset rxvco t1 rxvco t2 rxifb rxif tcxo fig. 7 receive section block diagram of CXA3003R 3. cdma low-pass filtering after mixing, the receive signal path splits into cdma and fm sections. for cdma, the baseband signal extends from 1 khz to 630 khz. frequency components above 750 khz are out-of-band for cdma operation. the mixers and the subsequent cdma low-pass filters combine to form the down-converter which outputs the cdma baseband signals. the passband, transition band, and rejection band characteristics of these low-pass filters, in conjunction with external if bandpass filtering, contribute to the ability of the receiver to select the desired baseband signals from the jamming effects of unwanted signals. the need to control the offset at the inputs of the adcs is critical to the receive signal path and the digital processing section. the offset control inputs : ioffset and qoffset, are provided for this purpose. 4. cdma analog-to-digital conversion analog i and q baseband components are converted to digital signals by the two identical 4-bit flash (parallel) adcs. the cdma adcs output a new digital value on each falling edge of the adc clock signal, chipx8. the chipx8 adc clock frequency of 9.8304 mhz is synthesized from the system crystal oscillator frequency of 19.68 mhz. the system crystal oscillator frequency is applied to the tcxo input of this ic. 5. fm receive signal path the receive signal path for fm operation is similar to that for cdma operation. differences lie in the characteristics of the i and q low-pass filters and the adcs. the if frequency is the same as in cdma (85.38 mhz), but the modulation can only extend ?5 khz from the if center frequency, forming a 30 khz wide channel. the low-pass filters for fm operation have a much lower bandwidth than those used in cdma. the offset of the fm low-pass filters is controlled just like the cdma low-pass filters by the ioffset and qoffset input pins. the lower bandwidth of the fm baseband signal gives rise to the use of very low power 8-bit successive- approximation adcs. the fm i and q analog baseband signals are sampled and held during the analog to digital (a/d) conversion process. the a/d conversion is initiated with a external strobe signal. a serial data stream is output beginning with the most significant bit (msb) of the result.
?4 CXA3003R 6. cdma transmit signal path this ic transmit signal path (see fig.8) accepts digital i and q baseband data from the digital processing section and outputs modulated if centered at 130.38 mhz to the rf transmitter. fig. 8 transmit section block diagram of CXA3003R 7. cdma digital to analog conversion and filters eight bits of i and q transmit data are input to the cdma digital to analog converters (dacs) by multiplexing over an 8-bit input port on the this ic. the transmit data rate is twice as fast as the differential transmit clock, txclk and txclkb. incoming data that is valid during the rising edge of the transmit clock is registered into the i dac. incoming data that is valid during the falling edge of the transmit clock is registered into the q dac. i and q transmit data values have been compensated in the digital processing section to account for their 1/2 clock cycle time difference. the frequency spectrum at the output of the cdma dacs contains unwanted frequency components due to dac output transition edges and transients. the transmit clock frequency and harmonics are found in the spectrum and are also undesirable. each cdma dac is followed by an anti-aliasing low-pass filter with a bandwidth of 630 khz that reduces unwanted frequency components. unlike the low-pass filters in the receive signal path, these do not require offset controls. 8. up-converting to if this ic transmit path outputs a differential if signal with cdma spread spectrum modulation extending ?30 khz from the transmit if center frequency of 130.38 mhz. the analog i and q baseband components from the cdma low-pass filters are mixed in quadrature with i and q lo signals at 130.38 mhz. after mixing, the i and q if components are summed and output differentially. the 130.38 mhz i and q lo signals are generated on this ic. the transmit vco is set to 260.76 mhz by an external varactor-tuned resonant tank circuit. an internal phase-lock loop and external loop filter network provides the feedback to the varactors which tune the vco precisely to 260.76 mhz. a master- slave divide-by-two circuit generates i and q signals in precise quadrature for the mixers. q dac 1/2 vco i dac cdma q tx lpf cdma i tx lpf fm tx lpf txclkb txclk txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 tcxo pd iset txifb txif fm mod tvco t2 tvco t1 pd out lock det pll pd
?5 CXA3003R 9. fm transmit signal path an analog fm modulation signal is constructed from 8-bit digital data supplied by the digital processing section. only the q-channel dac is used in this ic in fm mode, all other cdma circuits are disabled. the dac output is filtered by a low-pass anti-aliasing filter. the filtered dac output is the analog fm modulation signal, fm mod. this signal modulates the frequency of this ic transmit vco using external components when in fm rxtx mode. 10.operating modes this ic has several modes of operation. the cdma rxtx or fm rxtx modes are in effect when the telephone is making a call. idle mode is in effect when no call is in progress but the telephone receiver is active (ready to answer a call). sleep mode is a low-power mode in which the telephone cannot receive a call. this ic operating modes are defined by the states of three digital inputs: fmb, idleb, and sleepb. the power consumed by this ic is minimized by controlling these logic signals and disabling unused circuits. the selected circuits in this ic become active after the states of the operating mode controls are changed. 11.house keeping adc the house keeping adc provides dc measurement capability to the telephone. it is a low speed, 8-bit resolution, successive approximation analog-to-digital converter. it is designed to digitize dc voltages applied to the adcin pin from battery level, temperature, and other low frequency control or monitoring sensors. this adc is in a power-down state during normal operation. it is activated by a positive-going pulse on adcenbl. when this input is driven high, the house keeping adc powers up, samples and holds the voltage applied to adcin, and begins a conversion. the adc output is available from a serial digital interface. each of the eight data bits is valid (msb first) during the rising edge of the adcclk output. a rising edge of adcenbl during a conversion will be ignored. adcenbl must be low and a conversion completed before a new conversion can be started.
?6 CXA3003R notes of operation 1. signal operation the CXA3003R needs the master system clock ?cxo?that comes from a crystal oscillator at 19.68 mhz. a divide-by-4 derivative of tcxo called tcxo/4 operates as long as tcxo is active and power is applied to CXA3003R. transmit and receive if frequencies are generated by varactor-tuned tx and rx local oscillators on CXA3003R. chipx8, a derivative of tcxo is active for all operating modes except cdma sleep and fm idle. 2. receive if inputs the receive if inputs, rxif and rxifb, differentially drive a input stage within the CXA3003R. the differential input impedance is nominally 500 . the if signals receive by ac coupling. ac coupling capacitor values (0.001 ?) are chosen to maximize the power transfer from receive if circuitry. fig. 9 receive if inputs 3. transmit if outputs the transmit if outputs, txif and txifb, are differential outputs. the output impedance is low, 40 , nominally. these signals transfer to the subsequent transmit if circuitry by using ac coupling. ac coupling capacitor values (0.001 ?) are chosen to maximize the power transfer from the CXA3003R to the subsequent transmit if circuitry. fig. 10 transmit if outputs 6 7 CXA3003R from receive rf circuits CXA3003R 11 12 to transmit rf circuits
?7 CXA3003R 4. vcos in general terms, the frequency of oscillation, fo, for the vcos is determined by: fo = 1 2 lc where l and c are the net inductance and capacitance of the external resonant tank circuit. the resonant tank circuit comprises inductor l connected in parallel with capacitance c. the tank circuit is connected between rxvco t1 and rxvco t2 (shown in fig.11). another tank circuit is connected between txvco t1 and txvco t2 (shown in fig.12). the net capacitance of the tank circuit comprises a varactor diode (cv), an optional scaling capacitor connected (cv2) in parallel with the varactors, two dc blocking capacitors (cb) isolating the dc bias of the varactors from the CXA3003R, and pin-to-pin and pin-to-ground parasitic capacitors (cpp, cpg) (shown in fig.13). the net tank capacitance is found from c= (c v2 + 1/2 ?c v ) cb + (cpp + cpg ) (c v2 + 1/2 ?c v ) 2 + c b 2 fig. 11 receive vco fig. 12 transmit vco fig. 13 vco capacitors 5. transmit vco synthesizer the transmit synthesizer consists of a vco, a divide-by-two phase splitter, divide by r and n counters, and a phase detector. the vco and divide-by-two generate the i and q if signals used to up-convert analog baseband to if. the loop filter and tuning components are external to the CXA3003R. external pll circuit osc 2 3 80 CXA3003R vsc CXA3003R 16 17 15 19 18 40k fm tx lpf CXA3003R c v c v c v2 l c pp c pg c pg c b c b
?8 CXA3003R fig. 14 transmit vco synthesizer 6. transmit vco phase detector the phase detector output, pd out, is the output of a dual mode bi-directional charge pump. it provides two levels of output current for frequency acquisition (?75 ?) and phase lock maintenance (?6 ?) after the vco frequency is at or near its final frequency. the phase detector also provides a lock detect output, lock. this signal is low when unlocked, and high (high-impedance) when unused or in idle or sleep modes. lock will indicate the unlocked condition until the vco frequency is at its final value. lock will then toggle until phase lock has been established. the current available from pd out is set by an external resistor connected between pd iset and ground (shown in fig. 12). the value of the pd iset resistor is determined by r pd = 0.64/i o where io is the current available for maintaining the transmit vco frequency. during acquisition of the if frequency, the current limit from pd out increases to 11 times that set by the resistor on pd iset. a recommended io of 16.3 ? results in r pd =39 k ? %. 7. fm modulation scaling the fmmod output is used to frequency modulate the transmit vco. the output voltage swing on fm mod is normally 550 mvp-p. this modulating voltage must be scaled to achieve the required frequency deviation of the transmit vco frequency when the CXA3003R is operating in fm mode. a ?0 khz deviation of the transmit vco frequency translates into a ?5 khz deviation of the transmit if frequency. a simple resistive voltage divider may be used as long as the total load on fm mod is greater than 10 k . the output of the voltage divider drives the anode side of the varactor diodes (shown in fig. 12). vco phase detector divider 1/2 divider 1/106 to tx modulator 19.68mhz from tcxo n=16 lo pd out reference divider
?9 CXA3003R 8. tcxo the temperature-compensated crystal oscillator (tcxo) used in the telephone must provide a stable and accurate 19.68 mhz signal to the tcxo input of the CXA3003R. the specifications for this oscillator are outlined in table 1. table 1 tcxo oscillator requirements 9. adc and dac ranges all adcs and dacs on the CXA3003R have internally-generated references which eliminate the need for additional adjustment or calibration of the adcs and dacs. all adcs and dacs employ offset-binary coding (tables 2 and 3). the application of the house keeping adc is left up to the user. however, it can be useful for monitoring parameters such as battery voltage and temperature. the midpoint of the input voltage range of the house keeping adc is set to 1.5 v by an internal voltage reference. the input voltage range of the adc is 2.0 v. the gain of the adc approximately 7.8 v/step. table 2 adc output coding power supply voltage output level output load fout nominal frequency fout vs. temperature fout vs. power supply 3.3 v 0.8 vp-p min 10 k min 10 pf max 19.68 mhz ? ppm/? ?.3 ppm/v fout vs. load fout phase noise frequency control range control voltage range control voltage input impedance ?.2 ppm ?20 dbc/hz min (100 hz offset) 235?0 hz +0.5 tp +2.5 v 100 k min input voltage fm receive adc greater than positive full-scale positive full-scale 99.6 % of full-scale ? 50.2 % of full-scale 49.8 % of full-scale ? 0.4 % of full-scale negative full-scale less than negative full-scale house keeping adc >2.500 2.500 2.492 ? 1.504 1.496 ? 0.508 0.500 <0.500 input voltage cdma receive adc greater than positive full-scale positive full-scale 93.7 % of full-scale ? 53.3 % of full-scale 46.7 % of full-scale ? 6.7 % of full-scale negative full-scale less than negative full-scale output data msblsb 1111 1111 1111 1111 1111 1110 ? 1000 0000 0111 1111 ? 0000 0001 0000 0000 0000 0000 output data msb?sb 1111 1111 1110 1000 0111 0001 0000 0000
?0 CXA3003R table 3 dac input coding 10. adc offset control the external dc voltages connected to ioffset and qoffset pins control the output of the cdma and fm low-pass filters to the center of the cdma and fm adc input range, reducing the offset to zero. 11. receive low pass filters in CXA3003R, the receive low-pass filters remove residual if frequency components and present baseband i and q components to the adcs. the cdma baseband signal extends from 1 khz to 630 khz. the fm baseband signal extends from 100 hz to 14 khz. the low-pass filters reject frequency components above the passband while exhibiting a specific rate of attenuation in the transition band. for fm receive filters two external bypass capacitors are required between pin 31 and gnd,and between pin 32 and gnd as is shown in fig.15. fig. 15 fm receive filter 12. transmit signal path low-pass filters low-pass filters in the transmit signal path located after the transmit dacs attenuate much of the out-of- band frequency components created by digital-to-analog conversion process. these filters are relatively simple compared to the cdma and fm low-pass filters found in the receive signal path. since the gain of the transmit signal path is low, the offset at the filter outputs are less critical. transmit filter offsets are not controlled as offsets are in the cdma and fm receive paths. output voltage fm transmit dac positive full-scale 99.6 % of full-scale ? 50.2 % of full-scale 49.8 % of full-scale ? 0.4 % of full-scale negative full-scale input data msb??sb 1111 1111 1111 1110 ? 1000 0000 0111 1111 ? 0000 0001 0000 0000 0.01 0.01 31 32
?1 CXA3003R 13. power supply considerations, grounding, and decoupling the CXA3003R is targeted for use in battery operated cdma/fm portable cellular telephones. as such, the device has been designed to operate from a regulated 3.3 v power supply. the use of multiple voltage regulators is recommended throughout the telephone, but the CXA3003R should be powered from only one dedicated voltage regulator. individual voltage regulators are usually assigned to the major circuit subsections within the (i.e. receive rf, transmit rf, power amplifier, CXA3003R, etc.) to reduce the possibility of signals from one subsection interfering with or distorting signals from another subsection. the voltage regulator used in telephone for the CXA3003R should be a linear voltage regulator, not a switching regulator. this is to keep power supply noise on the CXA3003R power inputs as low as possible. the recommended power supply voltage range of the CXA3003R is from 3.13 to 3.47 v (3.3? %). it is recommended that a ? % accurate regulator be used so that the proper output voltage can be maintained over the temperature range of the telephone and over the power supply current range of the CXA3003R. power supply decoupling around the CXA3003R is done with 0.01 ? ceramic chip capacitors on each vdd pin. the capacitors are located as close to the pins as possible to minimize series inductance in the connection to the pin. the use of additional 0.001 ? decoupling capacitors in parallel with the 0.01 ? capacitors is recommended to further reduce high frequency noise on the power supply inputs to the CXA3003R. although the CXA3003R has both analog and digital circuits and separate digital power and ground pins a single ground plane is recommended. the ground plane must overlap the footprint of the CXA3003R as much as possible. all CXA3003R ground pins must be connected to the same analog ground plane.
sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy package structure 14.0 0.2 * 12.0 0.1 (0.22) 60 41 40 21 20 80 61 1 0.5 0.08 0.18 ?0.03 + 0.08 a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (13.0) 0.1 0.1 0.5 0.2 0?to 10 detail a 80pin lqfp (plastic) 0.5g lqfp-80p-l01 * qfp080-p-1212-a 0.1 note: dimension * ?does not include mold protrusion. package outline unit : mm ?2

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